What is not guaranteed

The command line prints this section last so it is what is left on your screen; the workbench shows it under Details → Not guaranteed. It is the difference between a board that routes and a board that works.

Said by the modelCopy Anchor Link

unsupported — anything the prompt asked for that the model could not do within the constraints, and anything it was not confident is correct. Published verbatim. An empty list on a hard prompt is itself a signal worth distrusting.

Gaps — what did not happenCopy Anchor Link

• A part with no orderable match in its package: dropped, and every net it was on loses that pin.
• A pin given as a number on a part whose symbol is known, or a pin that is not a pad and cannot be resolved.
• A net reduced to one pin, removed.
• A part whose symbol could not be found: its pin functions are unverified.

Notes — done, but worth sayingCopy Anchor Link

• A footprint taken from the vendor because the package is not one JLCPCB names: not IPC-verified, check it before ordering.
• A pinout borrowed from a pin-compatible family: assumed, not verified.
• A vendor footprint or 3D model that sits more than 0.35 mm from the nominal package at its best orientation, or whose orientation could not be checked.
• A part that is real but shows 0 stock today.
• Part figures reconciled between endpoints, or not confirmable.
• A relaxed schema on a backend that rejects a keyword.
• Parts a repair round removed rather than fixed.

Structural limitsCopy Anchor Link

• Two layers. Ground is poured on both outer layers where a fill can reach every ground pad, and routed as traces where it cannot (pour.judge stands the pour down and the notes say so); every other net is a trace. No inner layers, no controlled impedance, no length matching.
• Packages are limited to the supported list; parts over 48 pins are out of scope for a two-layer autoroute. MCU modules, LiPo chargers and USB-C PD are not covered yet and lose most of their parts.
• The placer optimises wirelength and edge connectors, and ranks its candidates by a routability model trained on the router's verdicts. It keeps copper from under a radio module's antenna where the footprint says where that is, and knows nothing else about thermal, EMI or mechanical fit.
• The router is freerouting. Via pad and drill are fixed measured numbers (0.60 / 0.30 mm); clearance is 0.20 mm unless a part's pads are closer, then that gap, down to the fab's 0.127 mm floor (dsn.rules); track width is per net, sized to IPC-2221 from the net's declared current and falling back to the 0.25 mm median when it declares none. It can leave a net incomplete — a pin its copper never reaches — and the pin is named; up to three placements are tried before the board is saved that way.
• The routability model predicts; it does not decide. The router runs on every build. The model orders the placements it sees, and where its first choice was confident and wrong the board says so.
• ERC reads the netlist, not the copper. DRC runs only when KiCad is installed.
• The electrical checks are only as good as what the design declared. Trace and via sizing, LED series resistors, resistor and regulator dissipation and capacitor ratings all need a net's voltage_v and current_a, and go silent rather than passing when those are missing. The board's notes name every power net that declared nothing, so a quiet check is never mistaken for a passing one.
• Copper is sized for steady-state temperature rise, to IPC-2221 on 1 oz outer copper at 10 °C. Nothing here models inrush, fusing current, copper resistance in series with a regulator, or a plane.
• 3D models are vendor geometry, not verified CAD.
• Stock and price are live snapshots at build time and move between quote and order.

What is checked by something other than the code that made itCopy Anchor Link

• Gerbers are read back by gerbonara.
• The .kicad_pcb is re-parsed and every pad compared with the placement; with KiCad installed its Gerber plot is cross-checked against ours and a DRC runs.
• Pin functions are resolved from the KiCad symbol library, never recalled.

Everything else in the pipeline is checked by code that also produced it, which is the fair criticism of a self-grading generator — and the reason the honest section exists.