Everything soldermask does

One line a feature, grouped by where it lives, each with the page that explains it. Compiled 18 Sep 2026 from the pages it points at; a feature that is not on one of those pages is not on this one either. The other lists in this tree are the layout map (by module), the CHANGELOG (by date, with the measurement) and what is not guaranteed (by limit).

A board starts fromCopy Anchor Link

• A sentence. A prompt on the home page's command line, the soldermask "<prompt>" command, or POST /api/projects. — Projects, CLI
• A design.json — the model's format, built without any model call; a file saved by the command line or edited by hand. — Projects, design.json
• A finished .kicad_pcb — read as it is in a fifth of a second: parts, positions and nets come across, the traces do not; nothing is designed, priced or routed unless asked; a board this pipeline cannot build is refused with the reason. — Projects
• A project .zip from another machine — every version, the draft and the conversation, imported as one project. — Exports
• A pinned microcontroller — @ on the command line lists five modules with live price and stock; the pinned one is a lookup by LCSC code, never a search. — Projects
• A blank project, named, whose first message builds v001. — Projects
• A fork of any version of any project, with parent recorded. — Versions
• Five seed prompts on an empty project that are known to build clean. — Chat

Design — the modelCopy Anchor Link

• Two backends, Gemini (default) and Claude, selected by SOLDERMASK_BACKEND or --backend, --model overriding the id, --effort for Claude; token usage and cost recorded. — Design
• A closed JSON schema the model is held to: intent, not footprints or part numbers; the search field is what to buy. — Design
• Function names for pins, never numbers; two-terminal parts take 1/2; modules are kind: module with package FROM_PART. — Design
• Priors measured from real boards in the system prompt: trace, clearance and via medians from 86 routed boards; component mix from 144 schematics; block idioms per IC from priors_blocks.json. — Design
• current_a and voltage_v on nets, the two numbers that size copper and enable Ohm's-law checks; a null is asked for rather than a guess. — Design
• unsupported, assumptions and decisions — what the prompt asked for that the model could not carry, published verbatim; a real architectural fork becomes two or three options with one recommended and built. — Design, Chat
• Schema relaxation is reported, not silent, when a backend rejects a keyword. — Design
• Conversation turns through the same call: a question is answered without a build; a change returns the complete revised design with surviving refdes kept. — Chat

PartsCopy Anchor Link

• A parametric index answers a value part exactly (100nF 0603) in 3.6 ms, 99 % correct@1 against 61 % for text search. — Parts
• Part-number normalisation — punctuation and packaging suffixes matched on a prefix, so a number written from memory still finds the part. — Parts
• JLCPCB's own catalogue on disk through their Parts API (soldermask setup --parts: the 7.25 M-record dump plus a detail record per stocked code, resumable), the jlcparts mirror without credentials, jlcsearch only as a last fallback with caching and a remembered failure. — Parts, CLI
• An empty local answer is the answer — no network round trip to the same data. — Parts
• The query ladder — phrase, part-number word, value, ordering suffix trimmed (never a trailing digit), generic term for the kind — with package fit, header pin count, category gate, and a preference order: in stock, category confirmed, pin count confirmed, basic before extended, more stock, price. — Parts
• An unresolved part is a gap, an outage is an outage — never a missing part. — Parts
• Basic vs extended parts counted at $3 setup each; the model asked to prefer basic. — Parts
• Supported packages: 17 hand-drawn IPC footprints plus every standard-named footprint from the imported KiCad corpus up to 48 pins, JLCPCB spellings canonicalised; each with pads, body, courtyard and a 3D profile. — Parts
• FROM_PART — the vendor's own footprint for a module, radio or radar, fetched from EasyEDA and cached; pads more than 0.35 mm off nominal reported. — Parts
• Alternates for a part that did not resolve, from parts sharing the exact KiCad pinout, marked safe only when the rated value matches. — Parts
• A chosen code is honoured: a component carrying lcsc is ordered as chosen and never searched again. — MCP

Symbols and pinsCopy Anchor Link

• The KiCad symbol library (203 libraries, vendored, indexed once) resolves pin function names to pad numbers. — Symbols
• Symbol matching by exact name or five-character prefix with a pin count within two; ICs and transistors matched, passives positional. — Symbols
• Two reported fallbacks: a pinout borrowed from a pin-compatible family (five voters, 90 % agreement) or the part's own EasyEDA symbol; no symbol at all is a gap. — Symbols
• Aliases and spellings: VIN/VI/VCC…, inversion markers, dashes, polarity signs, tokens of a decorated vendor name (PB0 in (PCINT0/CLKO/ICP1)PB0), a supply on several pads connected to all of them, the datasheet's names laid beside the vendor's, USB-C by position. — Symbols
• A raw pin number on a part with a known pinout is refused as unverifiable; multi-unit parts qualified A.OUT. — Symbols
• Symbol drawings for the schematic from the same library, with stock symbols for parts that have none. — Symbols

Checks before anything is placedCopy Anchor Link

• ERC — 23 rules from duplicate refdes to undriven-rail and led-no-resistor; errors block the exit status, warnings do not; nothing is silently fixed. — ERC
• Ohm's-law rules — LED series current, resistor and regulator dissipation against package ratings, capacitor voltage and derating — which stay silent when the voltage is undeclared and say so in the notes. — ERC
• Carrier gaps — a net routed narrower than the parts on it can drive (a 5.7 A MOSFET on a 0.25 mm trace), ratings read from the catalogue's typed attributes with MOSFETs from the description; gates, contact ratings and ground deliberately excluded. — ERC
• SPICE simulation in ngspice (binary or KiCad's library): rails switched on from zero, regulators, converters, op-amps, diodes, transistors and switches modelled; a rail against its declaration, LED currents and unmodelled parts reported; the deck kept in sim.json; report only, never the bar. — Simulation

PlacementCopy Anchor Link

• Simulated annealing on half-perimeter wirelength, courtyard overlap and edge pull for connectors; seeded, so a board regenerates exactly; incremental cost, bounding boxes cached. — Placement
• Six candidates a build, ordered by the routability model, the router shown up to three. — Placement
• Pinned parts — a placement can be an input, wholly or in part; a pinned part is never moved, turned or seated but stays in the cost. — Placement
• Antenna keepouts from a module's footprint, written for freerouting and as a KiCad rule area, and kept clear of parts by the placer on both sides; a part left in one is a gap. — Placement
• Both sides — surface-mount parts may go on the back when the front is out of room; connectors, switches, LEDs and antennas stay in reach; one mirroring convention across every writer and reader; board.sides = 1 forbids it. — Placement
• A precedent — the corpus is searched for a board with the same parts, and one anneal starts from its placement (a start, not a pin); listed on the board with repository and licence. — Placement
• The board grows to fit its parts unless board.fixed holds the outline. — Workbench
• A geometry rubric — the reviewer's rules this pipeline can measure (11 of 82 on 11 Sep 2026: decoupling distance, crystal distance, connectors at the edge, …), graded on every build, a bad grade one line in the notes; calibrated 32 of 38 against a professional's grades and checked against 3,021 designer revision pairs. — The rubric

RoutingCopy Anchor Link

• Two routers: the A* router (KiCadRoutingTools, Rust core, pinned by commit) first by default at 0.127/0.127 mm, freerouting 2.4.1 (Specctra DSN/SES, pinned jar) at 0.15/0.15; rules.router chooses the order. — Two routers
• A second opinion — when the first router leaves a pin unreached, the other routes the same placement and its copper is kept only if it reaches more pins. — Two routers
• The board's own clearance — read off the closest pad pair in any footprint, never below the fab's 0.127 mm floor, written to the DSN, the A* command line and the .kicad_pro and held equal by a test. — Placement, Two routers
• Track width per net to IPC-2221 from the declared current, a 0.25 mm measured floor, and a person's floor rules.min_track_mm that can only widen. — Placement
• A connectivity walk of the copper names the pins a net never reaches; retries up to three placements and keeps the least bad. — Placement
• Via and width reports — vias against the current they carry, wires against the width their net asked for; freerouting's pin-exit neck floored to the fab's minimum. — Placement, Two routers
• Exact sizes for the A* router, no via in a pad; freerouting's optimiser switched off. — Two routers
• Java found by running it, because macOS ships a stub; no router means an unrouted board with the reason printed. — Placement
• Deterministic — --route-only / Route again on an unchanged version reproduces the copper. — CLI

CopperCopy Anchor Link

• A ground pour on both outer layers on every board with a ground net: ground leaves the router, KiCad fills the zone, islands are stitched with vias, a pad the stitcher cannot reach is routed as its own net, and the pour stands down to routed ground — said — when it cannot fill. — Placement
• The fill KiCad computed is the copper the fab gets: read back from the filled board into the Gerbers, the picture and the page. — Placement
• Rounded corners — segments chained back into tracks, 45° vertices replaced by tangent arcs that are checked against every neighbour's copper and every pad they must still touch; real arcs in the .kicad_pcb, G02/G03 in the Gerber, both views. — Placement
• Hand copper as a constraint — tracks and vias drawn in the workbench go to the router as protected wiring; a half route is finished around, and the build says which of yours came back. — Placement
• DRC is the judge of the copper — kicad-cli's DRC with zones filled, not the router's own count; cosmetic findings counted separately by kind; a pour in pieces counted. — Placement

The verdict and the reportCopy Anchor Link

• One pass rule everywhere — repair.passes(): every part resolved, every net and connection the design asked for still there, no ERC errors, routed completely, copper clean under the pour; the CLI's VERDICT, the workbench's first pill, the evaluator's pass@1 and the MCP's verdict are the same number. — CLI, Repair and evaluation
• Four reporting channels — unsupported and assumptions on the design, gaps and notes on the board — published beside the result; a dropped request is treated as the bug. — Caveats
• Every stage reports what it could not do, in the CLI's order, in the workbench's chain, under the MCP's result. — Pipeline
• projects rejudge — kicad-cli's DRC run again over stored versions, the verdict rewritten where it moved and the first board.json kept beside it. — CLI
• A verdict is the build's, not a fresh DRC, and the page says so. — Projects

Fab outputCopy Anchor Link

• Gerbers written directly (RS-274X, FSLAX46Y46, no origin shift): copper, mask (+0.05 mm), silkscreen, paste, edge cuts, Excellon drill. — Fab files
• Read back by gerbonara, an independent library, and the result reported. — Fab files
• JLCPCB assembly files — BOM and CPL in their format, same millimetres as the Gerbers, Bottom for back parts. — Fab files
• Silkscreen drawings — one drawing per part in three places (Gerber, KiCad, screen): the vendor's own art for vendor footprints, generated outlines, pin-1 dots and polarity bars for the rest; clear of copper by construction. — Fab files
• The maker's mark — a filled ISO 3098 decal placed in the emptiest spot by one function, three lockups sized to the board; --no-mark / rules.mark leaves it off. — Fab files
• A stackup and a fabrication sheet — the vendor's 2/4/6-layer builds with every number daggered, and fourteen rows measured off the board (narrowest track, clearance, drill schedule, copper length); derived on read, no rebuild. — Fab files
• gerbers.zip, the fab package alone, from the History tab, the API or the MCP resource fab.zip. — Exports
• Stale layers cleared when several boards share an output directory. — Fab files

KiCad, schematic and 3DCopy Anchor Link

• A .kicad_pcb in KiCad 7's format (7–10 read it): footprints with LCSC and purpose properties, deterministic UUIDs, rule areas, the pour, every arc; the frame verified pad by pad to 0.1 µm against the placement. — KiCad and 3D
• A .kicad_sch written from the same sheet the workbench draws: library symbols, power ports, wires, junctions, labels, no-connects, PWR_FLAGs; read back geometrically and by kicad-cli sch export netlist + sch erc, net for net against the design. — KiCad and 3D
• A server-side schematic layout — roles per part, left-to-right flow read from pin types and net names, barycentre ordering, pull-ups above, decoupling below, wires only where they cross nothing. — Workbench
• Vendor 3D models for every LCSC part from EasyEDA, welded, centred, oriented from the pads, cached; meshes.json for the viewer and models/<lcsc>.wrl for KiCad from one mesh; primitives past 40,000 triangles. — KiCad and 3D
• With kicad-cli: DRC, a raytraced render, a GLB, and KiCad's own Gerber plot cross-checked against ours to 0.012 mm; --no-render keeps the DRC. — KiCad and 3D
• A .kicad_pro carrying the rule the board was routed at, so KiCad's DRC judges against it. — Placement

Stock and priceCopy Anchor Link

• Live stock at 1 / 10 / 25 / 100 by exact LCSC code with attrition, price breaks, setup fees, per-board cost, a risk per line (ok/tight/short/gone) and buildable-or-not per quantity; --qty on the CLI, a switch in the workbench. — Stock
• live vs cached said on the report. — Stock
• Stock headroom as runs (999+×), uncapped. — Stock

The app — projectsCopy Anchor Link

• The home page as a plane: ledger, command line, disc, foot; nothing scrolls but the ledger. — Projects
• Facets, filter and sort — All / Passes / Not orderable / From a file / Examples / Archived; name, summary, description, tags; recent, name, cost, versions. — Projects
• Example boards as flagged rows whose first action is Fork & edit. — Projects
• Live build state in the row — phase and seconds, from any device, refreshed every 3 s while a job runs. — Projects
• The disc: the board's skeleton drawn from board.svg, the verdict box, readout and version trail; Open, Fork, Export .zip, Rename, Archive, Delete to a trash that can restore. — Projects
• The foot: freerouting, A*, kicad-cli, model, catalogue, running jobs, boards, trash — each chip with why it is not green. — Projects
• Keyboard: j/k, arrows, Enter, f, /, Escape. — Projects
• About (version, commit, backend, router, data dir, changelog) and Benchmarks pages; the manual served at /docs. — App, Benchmarks

The app — workbenchCopy Anchor Link

• Three views — CU, 3D, SCH — at an address that is the board (/p/<project>/v004), keys 1/2/3, Tab cycles. — Workbench
• Four regions round the stage that fold and remember: thread and library left; layers, overlays, fab sheet, palette, nets and the picked thing right; summary, findings, scope, chain, history below; one info line at the foot. — Workbench
• Editor and Board palettes, a dimension grid, an active copper layer (Page Up/Down), the readout in millimetres. — Workbench
• Drag a part and it stays — a pin in constraints.pinned, honoured by the placer; net-aware snap, Alt to disable; arrows nudge a grid step, Shift ten; ⌘Z / ⇧⌘Z. — Workbench
• f flips a part to the back, refused with a reason where the placer's rule says it must stay in reach. — Workbench
• Hit-testing that reports — the part under the pointer outlined before the press, smallest box wins, tiny parts given a 12-px target. — Workbench
• Copper as an object — click a track for net, layer, width, length, who drew it; Del deletes yours, Take this track over makes the router's yours. — Workbench
• Copper stretches with a moved part; nets on a dragged part go faint with their ratsnest; poured nets have none. — Workbench
• Route a track yourself — x arms it; drag or click corners, two segments a click, v for a via, / or Space to flip the corner, Backspace, Enter, Esc; start from or join existing copper. — Workbench
• The stale bar and Rebuild — what is pinned and how much copper is from the last build; pins saved a second after you stop, a version only on rebuild. — Workbench
• Layer toggles with counts, net isolation, and a predicted congestion overlay from the routability model's heat head. — Workbench
• 3D: FR4, mask, gold, vendor models, orbit/pan/zoom pill, a five-face axis ball, parts on the back hung underneath. — Workbench
• SCH: drag a symbol (kept in constraints.sheet), drag a wire lane (constraints.wires), no-connect and one-pin marks. — Workbench
• Blocks — circuit fragments mined from finished boards (three boards by different people each), with evidence and whether they build; added as a proposal by net merge. — Workbench
• Parts palette — JLCPCB stock searched by number or kind, with whether this pipeline has a footprint for it; Choose… offers only pins the build will accept, pinned by LCSC code. — Workbench
• Proposals — a change is built and shown under an Accept / Discard bar with what it does (parts, nets, ERC delta, cost delta); scoped by selection; survives a reload. — Workbench
• Remove a part through the same gate, several at once, as a proposal. — Workbench
• The build log — one timed row per stage, live, kept with the turn, the same after a reload or on a second device. — Workbench
• The scope — an oscilloscope over sim.json: probe by selection, cursors A/B with Δt, frequency and ΔV, min/max drawn past two samples a pixel. — Workbench
• The chain — the build as boxes (design, resolve, sim, place, route, pour, check, fab, price), each with its time, readout and warnings; Simulate, Place again, Route again buttons. — Workbench
• The rack — eight knobs (router, seed, pour, precedent, mark, floor, sides, outline) saved as constraints; variations as saved sets recalled onto the next build. — Workbench
• The detail — the verdict pill and its clauses; Build (cost and stock table), Generation, Board, Parts; findings grouped Verdict, Electrical, Routing, Stock, Not guaranteed, Precedents, Live sync; a part's card with pins, turn and remove. — Workbench
• The readout — ERC, Route, Stock, Caveats and Sync as states with a rule under each. — Workbench

Chat and turnsCopy Anchor Link

• The thread is the project's record, read back from disk, the same on every device. — Chat
• A question builds nothing; a change is built; the reply carries a diff-computed changes line, not the model's account. — Chat
• Auto-repair — a build that is not clean is sent back to the model once and the revision built only if it scores better; both are versions; SOLDERMASK_AUTO_REPAIR. — Chat
• Decisions as cards under the reply; clicking one is the next turn. — Chat
• An edit builds on the version on screen, with a banner when that is not the newest. — Chat
• Four kinds of row — yours, the reply, a note turn the app started, a failed turn in red that stays on the record. — Workbench
• No model configured is said in the thread; design.json import still works. — Chat

Versions, history and filesCopy Anchor Link

• Immutable numbered versions per turn, never modified or deleted; one current version the next edit builds on; restore, label, notes, fork from here. — Versions
• Diffs computed from design.json, not the model's description, at the API too. — Versions
• Every file one click away — gerbers.zip, standalone.html (the workbench inlined, no server), .kicad_pcb, .kicad_sch, layers, BOM/CPL, board.svg, design.json, board.json, meshes.json, models/*.wrl, sim.json. — Exports
• Whole-project export and import as one zip (?chat=0 to leave the conversation out); refused with the member it stopped at; a design.json keeps its constraints on the way in. — Exports
• Which app version built each board recorded on the version. — Versions
• Projects on disk are a readable directory, migrated on read with a backup. — Projects on disk

Builds, sync and the phoneCopy Anchor Link

• Builds are jobs in a bounded worker pool: closing the tab does not stop one, one build per project at a time, a failure is a message. — Builds and sync
• Live sync between devices — view, camera, selection, net highlight, quantity and version over a per-project event stream, last write wins, capped and self-healing. — Builds and sync
• Phone layout — the board full-bleed, chat and details as sheets, Tilt orbiting by moving the phone, a web manifest for the home screen. — On your phone
• A QR code at startup that opens the app on a phone and logs it in. — On your phone

The command lineCopy Anchor Link

• soldermask "<prompt>" / --design with --out, --seed, --router, --qty, --repair N, --wire, --backend, --model, --effort, --project, --from, --no-sim, --no-pour, --no-precedent, --no-mark, --no-render. — CLI
• One stage at a time — --place-only, --route-only, --sim-only — all switches on one realise() call, held to one call by a test. — CLI
• The board drawn in the terminal before the verdict: an inline image in Ghostty, Kitty, WezTerm, iTerm2; braille elsewhere. — CLI
• VERDICT and then what this board does NOT guarantee, last so it stays on screen; exit status 1 on ERC errors. — CLI
• setup — finds Java and kicad-cli, fetches the router jar against its SHA-256, --parts takes the catalogue, --astar builds the second router, --check reports. — CLI
• projects list | show | fork | revert | rejudge. — CLI
• serve with port, host, TLS or --http, token or --no-auth, --proxy, --workers, --log-file. — CLI
• version, release note | show | bump, docs (build and live-reload), banner. — CLI
• mcp, mcp --tools, mcp --http, mcp keys add | list | revoke. — CLI
• learn status | generate | train | report | relabel (and redraw, crossval, backfill, ablate). — CLI
• python -m soldermask.evaluate and python -m soldermask.repair. — CLI
• Colour and banner rules (NO_COLOR, FORCE_COLOR, 24-bit where the terminal has it). — CLI

The HTTP APICopy Anchor Link

• Everything the pages do — health, app state, changelog, benchmarks, platforms and their meshes. — API
• Projects — list, create (blank, prompt, design, kicad), detail with the thread, patch, delete, fork, export.zip, import, chat, import a design or a .kicad_pcb, jobs. — API
• Constraints — get, put (validates, builds nothing), delete, the sheet, rebuild, variations (save, rename, forget, recall), route again, simulate a version. — API
• Jobs — status, phase, timed steps, result. — API
• Parts and blocks — search stock, resolve one part's pins, add a part, remove parts, the block library, add a block. — API
• Proposals — propose with a scoped selection, read, the proposal's board, accept, reject. — API
• Versions — metadata and diff, label and notes, restore, board.json, design.json, files, one file, gerbers.zip, inspector.html. — API
• Trash — list, restore, empty. — API
• Live events — a server-sent stream per project. — API

The MCP serverCopy Anchor Link

• Thirteen tools, no model inside: status, design_brief, search_parts, pins, check_design, place, score_placement, precedent, build, rebuild, verdict, drc, projects; every result with verdict, gaps, notes. — MCP
• Interoperability at the stages — a caller can hand in its own design, parts (lcsc), placement, hand copper and knobs, and is judged by the same judge. — MCP
• Resources — the design and constraints schemas, the package list, these docs, every file of every version, fab.zip as a blob. — MCP
• Progress notifications per stage so a client's timeout does not fire mid-route. — MCP
• --http — Streamable HTTP with bearer keys, one directory per key, one build slot, Origin check, digests on disk; keys added and revoked while it runs. — MCP
• A remote client is told what it cannot have — a precedent under a non-permissive licence is withheld and named. — MCP
• Hand-written server, three protocol versions, stdout kept clean; tests/test_mcp.py counts the realise() calls. — MCP

Serving, security, operationsCopy Anchor Link

• Hypercorn with TLS by default — a self-signed LAN certificate, HTTP/2, graceful shutdown. — Production
• Access token generated once, exchanged for a cookie, five-strike lockout, --proxy for a reverse proxy, --no-auth. — Access control
• Hardening — CSP with nonces, HSTS, frame and content-type headers, body and message limits. — Production
• No third-party requests — three.js and fonts vendored; the app works with no internet. — Production
• Observability — timed access log, Server-Timing, /api/health, /about. — Production
• Deploy recipes — launchd, systemd, nginx, containers, backups; upgrading migrates projects with a backup. — Deploying
• Routing on a bigger machine — tools/remote_route.sh puts a corpus pass on a spot VM and brings the corpus home; SOLDERMASK_ANNEAL_WORKERS and SOLDERMASK_ROUTE_WORKERS are the build's two parallelism switches. — Remote routing
• Everything is an environment variable — home, projects, cache, docs, backend, keys, token, corpus, jar, model file. — Configuration
• A troubleshooting page for every pill and message. — Troubleshooting

Repair, the wiring turn and evaluationCopy Anchor Link

• --repair N — the pipeline's findings sent back as a brief; a dropped part scored worse than an unresolved one so repair cannot launder; repair.json records the gain and the parts lost. — Repair
• The wiring turn (--wire) — after parts resolve, the model wires them against the exact pin names the ordered parts have, under a schema in which a wrong pin cannot be written; a wrong part goes back with a better search once. — Repair
• soldermask.evaluate — sixty prompts in four tiers, pass@1 per tier and pooled, every measured field per row, deterministic replays from saved designs, --wire, --repair, --rescore under today's rule with the first number kept. — Evaluation
• The harness keeps itself honest — --no-route drops routability from the rule rather than scoring zero; a row whose verdict disagrees with the build's is refused. — Evaluation
• A benchmarks page that computes nothing — model card, clean-placement payoff, calibration, ensemble seeds, heat head, pipeline runs by tier, the human rubric, Mendicant, the GNN, the router A/B; training-day numbers labelled as such; corrections kept in place. — Benchmarks

The corpus and the routability modelCopy Anchor Link

• Every route the pipeline runs is kept as a labelled example — placement, router, rule, judge, pour, verdict — in .cache/corpus; 64,122 examples of 15,951 boards on 18 Sep 2026. — Routability
• learn generate anneals and routes boards for hours on N workers; learn train fits the CNN (ISOnet) and two logistic baselines; learn report, relabel, redraw, crossval, ablate. — CLI, Routability
• Eight congestion maps and 23 scalars per placement, the genome IR, layer count as a scalar. — Routability
• A calibrated probability with intervals, every board family held out once; between-board and within-board reported separately, the within-board null said plainly. — Routability
• A heat head predicting where copper will crowd and which pins go unreached, shown as an overlay. — Routability
• A second router's labels kept apart from the first's (learn train --router). — Two routers
• A bank of open-hardware boards with licences recorded, indexed for precedents. — Routability
• The model file is swappable (SOLDERMASK_ROUTABILITY) and refuses to rate a poured board, falling back to the analytic estimate and saying so. — Configuration, Placement

Research instruments (not in the build)Copy Anchor Link

• The rubric — the geometry grader and its calibration against a professional and against 3,021 revision pairs. — The rubric
• Mendicant — a placement folded as RNA and a Physarum mould as unfitted routability instruments, with a Rust core (mould/) held to the numpy reference at 1e-9. — Physarum
• A graph judge (GNN) against the CNN on the same within-board population. — Benchmarks
• Router A/B over the whole bank, two routers under one DRC judge. — Two routers
• Photonics — the fold-ordered placer against a photonic router's judge. — Photonics
• Two papers written from the corpus, paper/isonet.tex and paper/mendicant.tex. — Research

What it does not doCopy Anchor Link

Two layers, 48 pins a part, 150 mm, 120 footprints; no inner layers, controlled impedance or length matching; no thermal, EMI or mechanical fit; ERC reads the netlist and not the copper; the electrical checks are only as good as what the design declared; 3D models are vendor geometry; stock and price are snapshots. The full list, with what is checked by something other than the code that made it, is What is not guaranteed.